View DS2764AE025_4945008.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 20 011806 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds2764 high-precision li+ battery monitor is a data-acquisition, information-storage, and safety- protection device tailored for cost-sensitive battery pack applications. this low-power device integrates precise temperature, voltage, and current measurement, nonvolatile (nv) data storage, and li+ protection into the small footprint of either a tssop package or flip-chip package. the ds2764 is a key component in applications requiring remaining capacity estimation, safety monitoring, and battery- specific data storage. pin configurations features li+ safety circuit overvoltage protection overcurrent/short-circuit protection undervoltage protection 0v battery recovery charge available in two configurations: internal 25m sense resistor external user-selectable sense resistor current measurement 12-bit bidirectional measurement internal sense resistor configuration: 0.625ma lsb and 1.9a dynamic range external sense resistor configuration: 15.625 v lsb and 64mv dynamic range current accumulation: internal sense resistor: 0.25mahr lsb external sense resistor: 6.25 vhr lsb voltage measurement with 4.88mv resolution temperature measurement using integrated sensor with 0.125c resolution 40 bytes of lockable eeprom option for unique 64-bit id industry 2-wire interface with programmable slave address low-power consumption: active current: 60 a typ, 90 a max sleep current: 1 a typ, 2 a max applications pdas cell phones/smartphones digital cameras ordering information part temp range pin-package ds2764be+ -20c to +70c 16 tssop selector guide appears at end of data sheet, for additional options. ds2764 high-precision li+ battery monito r with 2-wire interface www.maxim-ic.com top view c c v in v dd scl v ss v ss v ss sda is1 tssop is2 sns sns 1 2 2 3 2 1 4 5 6 7 8 16 15 14 13 12 11 10 9 sns p s pls d c flip chip (top view bumps on bottom) pls dc is2 c c p s v in is1 v dd scl sda sns v ss 1 2 3 4 a b c d e f sns probe v ss probe
ds2764 high-precision li+ battery monitor with 2-wire interface 2 of 20 absolute maximum ratings voltage range on pls and cc pins, relative to v ss -0.3v to +18v voltage range on any other pin, relative to v ss -0.3v to +6v continuous internal sense resistor current 2.5a pulsed internal sense resistor current 50a for <100s/s, <1000 pulses operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/jedec j-std-020a specification stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device. recommended dc operating conditions (2.5v v dd 5.5v, t a = -20c to +70c.) parameter symbol conditions min typ max units supply voltage v dd (note 1) 2.5 5.5 v voltage sense input v in (note 1) -0.3 v dd + 0.3 v serial interface pins scl, sda (note 1) -0.3 +5.5 v dc electrical characteristics (2.5v v dd 5.5v, t a = -20c to +70c.) parameter symbol conditions min typ max units active current i active scl = sda = v dd , normal operation 60 90 a sleep mode current i sleep scl = sda = 0v, no activity, ps floating 1 2 a input logic high: scl, sda v ih (note 1) 1.5 v input logic high: ps v ih (note 1) 0.7 x v dd v input logic low: scl, sda v il (note 1) 0.4 v input logic low: ps v il (note 1) 0.3 x v dd v output logic high: cc v oh i oh = -0.1ma (note 1) v pls - 0.4 v output logic high: dc v oh i oh = -0.1ma (note 1) v dd - 0.4 v output logic low: cc v ol_cc i ol = 0.1ma (note 1) 0.4 v output logic low: dc v ol_dc i ol = 0.5 a (note 1) 0.4 v output logic low: sda v ol i ol = 4ma (note 1) 0.4 v pulldown current: scl, sda i pd 1 a input resistance: v in r in 5 m internal current-sense resistor r sns +25c 20 25 30 m bus low to sleep time t sleep 2.1 s
ds2764 high-precision li+ battery monitor with 2-wire interface 3 of 20 electrical characteristics: protection circuitry (2.5v v dd 5.5v, t a = 0c to +50c.) parameter symbol conditions min typ max units 4.325 4.350 4.375 overvoltage detect v ov (notes 1, 2) 4.250 4.275 4.300 v charge enable v ce (note 1) 4.10 4.15 4.20 v undervoltage detect v uv (note 1) 2.5 2.6 2.7 v overcurrent detect i oc (note 3) 1.8 1.9 2.0 a overcurrent detect v oc (notes 1, 4) 45 47.5 50 mv short-circuit detect i sc (note 3) 5.0 8.0 11 a short-circuit detect v sc (notes 1, 4) 150 200 250 mv overvoltage delay t ovd 0.8 1 1.2 s undervoltage delay t uvd 90 100 110 ms overcurrent delay t ocd 5 10 20 ms short-circuit delay t scd 160 200 240 s test threshold v tp 0.5 1.0 1.5 v test current i tst 5 20 40 a electrical characteristics: temperature, voltage, current (2.5v v dd 5.5v, t a = -20c to +50c.) parameter symbol conditions min typ max units temperature resolution t lsb 0.125 c temperature full-scale magnitude t fs 127 c temperature error t err (note 5) 3 c voltage resolution v lsb 4.88 mv voltage full-scale magnitude v fs 4.75 v voltage gain error v gerr 5 % (note 3) 0.625 ma current resolution i lsb (note 4) 15.625 v (notes 3, 6) 1.9 2.56 a current full-scale magnitude i fs (note 4) 64 mv current offset error i oerr (note 7) 1 lsb (notes 3, 8, 9) 10 current gain error i gerr (note 4) 2 % (note 3) 0.25 mah accumulated current resolution q ca (note 4) 6.25 vhr current sampling frequency f samp 1456 hz t err1 (note 10) 1 3 % internal timebase accuracy t err2 (note 10) 6.5 %
ds2764 high-precision li+ battery monitor with 2-wire interface 4 of 20 electrical characteristics: 2-wire interface (2.5v v dd 5.5v, t a = -20 c to +70 c.) parameter symbol conditions min typ max units scl clock frequency f scl (note 12) 0 100 khz bus free time between a stop and start condition t buf 4.7 s hold time (repeated) start condition t hd:sta (note 13) 4.0 s low period of scl clock t low 4.7 s high period of scl clock t high 4.0 s setup time for a repeated start condition t su:sta 4.7 s data hold time t hd:dat (note 14, 15) 0 5.0 s data setup time t su:dat (note 14) 250 ns rise time of both sda and scl signals t r 1000 ns fall time of both sda and scl signals t f 300 ns setup time for stop condition t su:sto 4.0 s spike pulse widths suppressed by input filter t sp (note 16) 0 50 ns capacitive load for each bus line c b (note 17) 400 pf scl, sda input capacitance c bin 60 pf eeprom reliability specification (2.5v v dd 5.5v, t a = -20 c to +70 c.) parameter symbol conditions min typ max units copy to eeprom time t eec 2 10 ms eeprom copy endurance n eec (note 11) 25,000 cycles note 1: all voltages are referenced to v ss . note 2: see the selector guide section to determine the corresponding part number for each v ov value. note 3: internal current-sense resistor configuration. note 4: external current-sense resistor configuration. note 5: self-heating due to output pin loading and sense resistor power dissipation can alter the reading from ambient conditions. note 6: compensation of the internal sense resistor value for initial tolerance and temperature coefficient of -20c to +70c can reduc e the maximum reportable magnitude to 1.9a. note 7: current offset error null to 1 lsb typically requires 3.5s in-system calibration by user. note 8: current gain error specification applies to gain error in converting the voltage difference at is1 and is2, and excludes any er ror remaining after the ds2764 compensates for the internal sense resistor?s temperature coefficient of 3700ppm/ c to an accuracy of 500ppm/ c. the ds2764 does not compensate for external sense resistor characteristics, and any error terms arising from the use of an external sense resistor should be taken into account when calculating total current measurement error. note 9: accuracy at time of shipment from dallas semiconductor is 3% max. board mounting processes may cause the current gain error to widen to as much as 10% for devices with the internal sense resistor option. contact factory for on-board recalibratio n procedure devices with the internal sense resistor option to improve accuracy. note 10: typical value for t err1 is specified at 3.6v and +25c, max value is specified for 0c to +50c. max value for t err2 is specified for -20c to +70c. note 11: four-year data retention at +70 c. note 12: timing must be fast enough to prevent the ds2764 from entering sleep mode due to bus low for period > t sleep note 13: f scl must meet the minimum clock low time plus the rise/fall times.
ds2764 high-precision li+ battery monitor with 2-wire interface 5 of 20 note 14: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 15: this device internally provides a hold time of at least 300 ns for the sda signal (referred to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 16: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instant. note 17: c b total capacitance of one bus line in pf. figure 1. i 2 c bus timing diagram sda scl t f t r t su;dat t low s t hd;sta t hd;dat t f t su;sta t hd;sta t su;sto t r t buf t sp sr p s i 2 c is a trademark of philips corp. purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associate d companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
ds2764 high-precision li+ battery monitor with 2-wire interface 6 of 20 pin description pin tssop flip chip symbol function 1 c1 cc charge protection control output. controls an external p-channel high-side charge protection fet. 2 b1 pls battery pack positive terminal input. the ds2764 monitors the pack plus terminal through pls to detect overload and short circuit removal, as well as the presence or removal of a charge source. additionally, a charge path to recover a deeply depleted cell is provided from pls to v dd . in sleep mode, any capacitance or voltage source connected to pls is discharged internally to v ss through 200 a (nominal) to assure reliable detection of a valid charge source. for details of other internal connections to pls and associated conditions see the li+ protection circuitry section. 3 b2 dc discharge protection control output. controls an external p-channel high-side discharge protection fet. 4, 5, 6 a3 sns sense resistor connection. connect to the negative terminal of the battery pack. in the internal sense resistor configuration, the sense resistor is connected between v ss and sns. 7 c4 ps power switch sense input. the device wakes up from sleep mode when it senses the closure of a switch to v ss on this pin. pin has an internal 1 a pull-up to v dd . 8 b4 is2 current-sense input. this pin is internally connected to sns through a 4.7k resistor. 9 d4 is1 current-sense input. this pin is internally connected to v ss through a 4.7k resistor. connect a 0.1 f capacitor between is1 and is2 to complete a low pass input filter. 10 e4 sda serial data input/out. 2-wire data line. open-drain output driver. connect this pin to the data terminal of the battery pack. pin has an internal 1 a pulldown for sensing disconnection. 11, 12, 13 f3 v ss device ground. connect directly to the negative terminal of the li+ cell. for the external sense resistor configuration, connect the sense resistor between v ss and sns. 14 e2 scl serial clock input. 2-wire clock line. input only. connect this pin to the clock terminal of the battery pack. pin has an internal 1 a pulldown for sensing disconnection. 15 e1 v dd power-supply input. connect to the positive terminal of the li+ cell through a decoupling network. 16 d1 v in voltage sense input. the voltage of the li+ cell is monitored through this input pin. this pin has a weak pull-up to v dd . ? c2 sns probe do not connect. ? d2 v ss probe do not connect.
ds2764 high-precision li+ battery monitor with 2-wire interface 7 of 20 figure 2. block diagram detailed description the ds2764 high-precision li+ battery monitor is a data-acquisition, information-storage, and safety-protection device tailored for cost-sensitive battery pack applications. this low-power device integrates precise temperature, voltage, and current measurement, nonvolatile (nv) data storage, and li+ protection into the small footprint of either a tssop package or flip-chip package. the ds2764 is a key component in applications including remaining capacity estimation, safety monitoring, and battery-specific data storage. through its 2-wire interface, the ds2764 gives the host system read/write access to status and control registers, instrumentation registers, and general-purpose data storage. the 7-bit slave address is field programmable, thus allowing up to 128 devices to be distinctly addressed by the host system. the ds2764 is capable of performing temperature, voltage, and current measurement to a resolution sufficient to support process monitoring applications such as battery charge control, remaining capacity estimation, and safety monitoring. temperature is measured using an on-chip sensor, eliminating the need for a separate thermistor. bidirectional current measurement and accumulation are accomplished using either an internal 25m sense resistor or an external device. eeprom memory is provided to save important battery data in true nv memory that is unaffected by severe battery depletion, accidental shorts, or esd events. 40 bytes are partitioned into two 16-byte blocks and one 8-byte block. each block can be individually locked or write protected to provide additional security for unchanging battery data. the lock operation is permanent and thus converts rewritable eeprom to read only memory. devices ordered with the unique 64-bit id option do not have access to the 8 byte block, only the two 16 byte blocks of eeprom are available. 2-wire interface thermal sense mux voltage reference adc registers and user memory 25m sd a chip ground + - lockable eeprom temperature voltage current accum. current status/control li+ protection v in is1 is2 sns is2 is1 v ss c c d c pls ps timebase internal sense resistor configuration only ds2764 scl
ds2764 high-precision li+ battery monitor with 2-wire interface 8 of 20 figure 3. application example note 1: r sns is present for external sense resistor configurations only. note 2: r sns-int is present for internal sense resistor configurations only. sns ds2764 v ss is2 is1 4.7k 4.7k voltage sense r sns-int (note 2) r ks r ks c c pls d c sns sns sns p s is2 v in v dd scl v ss v ss v ss sda is1 ds2764 104 102 x 2 104 pack+ pack- ps 4.7k 150 1k 150 1k 1k 102 bat+ bat- r sns (note 1) data 150 clock 150
ds2764 high-precision li+ battery monitor with 2-wire interface 9 of 20 power modes the ds2764 has two power modes: active and sleep. while in active mode, the ds2764 continually measures current, voltage, and temperature to provide data to the host system and to support current accumulation and li+ safety monitoring. in sleep mode, the ds2764 ceases these activities. the ds2764 enters sleep mode when any of the following conditions occurs: the pmod bit in the status register has been set to 1 and both scl and sda are low for longer than 2.1s (pack disconnection). the voltage on v in drops below undervoltage threshold v uv for t uvd (cell depletion). the ds2764 returns to active mode when any of the following occurs: the pmod bit has been set to 1 and either the sda or scl line is pulled high (pack connection). the ps pin is pulled low (power switch). the voltage on pls becomes greater than the voltage on v dd (charger connection). the ds2764 defaults to active mode when power is first applied. li+ protection circuitry during active mode, the ds2764 constantly monitors cell voltage and current to protect the battery from overcharge (overvoltage), overdischarge (undervoltage), and excessive charge and discharge currents (overcurrent, short circuit). conditions and ds2764 responses are described in the following sections and summarized in table 1 and figure 4. table 1. li+ protection conditions and ds2764 responses activation condition threshold delay response release threshold overvoltage v in > v ov t ovd cc high v in < v ce , or v is -2mv undervoltage v in < v uv t uvd cc, dc high, sleep mode v pls > v dd (1) (charger connected) overcurrent, charge v is > v oc (2) t ocd cc, dc high v pls < v dd - v tp (3) overcurrent, discharge v is < -v oc (2) t ocd dc high v pls > v dd - v tp (4) short circuit v sns > v sc t scd dc high v pls > v dd - v tp (4) v is = v is1 - v is2 . logic high = v pls for cc and v dd for dc . all voltages are with respect to v ss . i sns references current delivered from pin sns. note 1: if v dd < 2.2v, release is delayed until the recovery charge current passed from pls to v dd charges the battery and allows v dd to exceed 2.2v. note 2: for the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: i sns > i oc for charge direction and i sns < -i oc for discharge direction. note 3: with test current i tst flowing from pls to v ss (pulldown on pls). note 4: with test current i tst flowing from v dd to pls (pullup on pls). overvoltage. if the cell voltage on v in exceeds the overvoltage threshold, v ov , for a period longer than overvoltage delay, t ovd , the ds2764 shuts off the external charge fet and sets the ov flag in the protection register. when the cell voltage falls below charge enable threshold v ce , the ds2764 turns the charge fet back on (unless another protection condition prevents it). discharging remains enabled during overvoltage, and the ds2764 re-enables the charge fet before v in < v ce if a discharge current of -80ma (v is -2mv) or less is detected. undervoltage. if the voltage of the cell drops below undervoltage threshold, v uv , for a period longer than undervoltage delay, t uvd , the ds2764 shuts off the charge and discharge fets, sets the uv flag in the protection register, and enters sleep mode. the ds2764 provides a recovery charge path from pls to v dd to power the ds2764 by the charger when the cell is severely depleted. once the ds2764 regains power it will enter active mode of operation and allow full charging of the cell. the recovery charge path is disabled when the cell voltage is above 3.0v to prevent cell overcharge through the pls pin.
ds2764 high-precision li+ battery monitor with 2-wire interface 10 of 20 overcurrent, charge direction. the voltage difference between the is1 pin and the is2 pin (v is = v is1 - v is2 ) is the filtered voltage drop across the current-sense resistor. if v is exceeds overcurrent threshold v oc for a period longer than overcurrent delay t ocd , the ds2764 shuts off both external fets and sets the coc flag in the protection register. the charge current path is not re-established until the voltage on the pls pin drops below v dd - v tp . the ds2764 provides a test current of value i tst from pls to v ss to pull pls down to detect the removal of the offending charge current source. overcurrent, discharge direction. if v is is less than -v oc for a period longer than t ocd , the ds2764 shuts off the external discharge fet and sets the doc flag in the protection register. the discharge current path is not re- established until the voltage on pls rises above v dd - v tp . the ds2764 provides a test current of value i tst from v dd to pls to pull pls up to detect the removal of the offending low-impedance load. short circuit. if the voltage on the sns pin with respect to v ss exceeds short-circuit threshold v sc for a period longer than short-circuit delay t scd , the ds2764 shuts off the external discharge fet and sets the doc flag in the protection register. the discharge current path is not re-established until the voltage on pls rises above v dd - v tp . the ds2764 provides a test current of value i tst from v dd to pls to pull pls up to detect the removal of the short circuit. figure 4. li+ protection circuitry example waveforms summary. all of the protection conditions described above are or?ed together to affect the cc and dc outputs. dc = (undervoltage) or (overcurrent, either direction) or (short circuit) or (protection register bit de = 0) or (sleep mode) cc = (overvoltage and v is -2mv) or (undervoltage) or (overcurrent, charge direction) or (protection register bit ce = 0) or (sleep mode) soft startup. the discharge protection fet is turned on slowly when the ds2764 enters active mode from sleep. the soft startup reduces the inrush current that normally occurs when a battery pack is inserted into an un-powered host system. soft startup does not reduce inrush currents if the ds2764 is already in active mode when the battery pack is connected to the un-powered system. mode v ov v ce v uv v cell v is charge discharge cc dc -v sc v oc -v oc 0 t scd t ocd t ocd t uvd t ovd v pls v dd active v ss v ss sleep t ovd (note 1) note 1: to allow the device to react quickly to short circuits, detection occurs on the sns pin rather than on the filtered is1 and is2 pins. the actual short-circuit detect condition is v sns > v sc .
ds2764 high-precision li+ battery monitor with 2-wire interface 11 of 20 current measurement in active mode, the ds2764 continually measures the current flow into and out of the battery by measuring the voltage drop across a current-sense resistor. the ds2764 is available in two configurations: 1) internal 25m current-sense resistor and 2) external user-selectable sense resistor. in either configuration, the ds2764 considers the voltage difference between pins is1 and is2 (v is = v is1 - v is2 ) to be the filtered voltage drop across the sense resistor. a positive v is value indicates current is flowing into the battery (charging), while a negative v is value indicates current is flowing out of the battery (discharging). v is is measured with a signed resolution of 12 bits. the current register is updated in two?s-complement format every 88ms with an average of 128 readings. current measurements outside the register range are reported at the range limit. each measurement is internally compensated for offset on a continual basis minimizing error resulting from variations in device temperature and voltage. figure 5 shows the format of the current register. for the internal sense resistor configuration, the ds2764 maintains the current register in units of amps, with a resolution of 0.625ma and full-scale range of no less than 1.9a (see note 7 on i fs spec for more details). the ds2764 automatically compensates for internal sense resistor process variations and temperature effects when reporting current. for the external sense resistor configuration, the ds2764 writes the measured v is voltage to the current register, with a 15.625 v resolution and a full-scale 64mv range. figure 5. current register format msb?address 0e lsb?address 0f s 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x msb lsb msb lsb units: 0.625ma for internal sense resisto r 15.625 v for external sense resisto r current accumulator the current accumulator facilitates remaining capacity estimation by tracking the net current flow into and out of the battery. current flow into the battery increments the current accumulator while current flow out of the battery decrements it. data is maintained in the current accumulator in two?s-complement format. figure 6 shows the format of the current accumulator. when the internal sense resistor is used, the ds2764 maintains the current accumulator in units of amp-hours, with a 0.25mahrs resolution and full-scale 8.2ahrs range. when using an external sense resistor, the ds2764 maintains the current accumulator in units of volt-hours, with a 6.25 vhrs resolution and a full-scale 205mvhrs range. the current accumulator is a read/write register that can be altered by the host system as needed. figure 6. current accumulator format msb?address 10 lsb?address 11 s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb units: 0.25mahrs for internal sense resisto r 6.25 vhrs for external sense resisto r
ds2764 high-precision li+ battery monitor with 2-wire interface 12 of 20 current offset compensation the current measurement and current accumulation are internally compensated for offset on a continual basis minimizing error resulting from variations in device temperature and voltage. additionally, the current offset bias register is a user programmable constant bias that can be used to alter the offset of the current and accumulated current registers. user programmed bias values can be used to correct for offset errors after final assembly of the module or pack. an offset value can be purposely chosen to bias current accumulation in the discharge polarity to ensure a pessimistic accounting of a level standby currents. the current offset bias value resides in eeprom address 33h in two?s-complement format and is subtracted from current measurements during the accumulation process. the current offset bias is applied to the internal and external sense resistor configurations. the factory default for eeprom address 33h is 0. figure 7. current offset bias address 33 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb units: 0.625ma for internal sense resisto r 15.625 v for external sense resisto r voltage measurement the ds2764 continually measures the voltage between pins v in and v ss over a 0 to 4.75v range. the voltage register is updated in two?s-complement format every 3.4ms with a 4.88mv resolution. voltages above the maximum register value are reported as the maximum value. figure 8 shows the voltage register format. figure 8. voltage register format msb?address 0c lsb?address 0d s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb msb lsb units: 4.88mv temperature measurement the ds2764 uses an integrated temperature sensor to continually measure battery temperature. temperature measurements are placed in the temperature register every 220ms in two?s-complement format with a 0.125c resolution over a 127c range. figure 9 shows the temperature register format. figure 9. temperature register format msb?address 18 lsb?address 19 s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb msb lsb units: 0.125 c
ds2764 high-precision li+ battery monitor with 2-wire interface 13 of 20 power switch input the ds2764 provides a power control function that uses the discharge protection fet to gate battery power to the system. the ps pin, internally pulled to v dd through a 1 a current source, is continuously monitored for a low- impedance connection to v ss . if the ds2764 is in sleep mode, the detection of a low on the ps pin causes the device to transition into active mode, turning on the discharge fet. if the ds2764 is already in active mode, activity on ps has no effect on the fet control. the host system has the option of monitoring activity on the ps pin by reading the ps bit in the special feature register. the ps bit latches a 0 value when a logic low occurs on the ps pin regardless of the operating mode of the ds2764. if the host intends to monitor future ps pin events, it must write a 1 to the ps bit to ensure that a subsequent low forced on the ps pin is latched into the ps bit. the ps bit value has no effect on operation of the ds2764 and can be ignored if ps pin monitoring is not required. memory the ds2764 has a 256-byte linear address space. registers for instrumentation, status, and control are mapped in the lower 32 bytes, with lockable eeprom blocks and the unique rom id occupying portions of the remaining address space. the function command register occupies location feh. all eeprom memory is general purpose except byte addresses 31h, 32h and 33h, which should be written with the default values for the status register, 2- wire slave address and current offset register, respectively. when reading two-byte registers, (current, acr, voltage and temperature), the msb should be read first. when the msb of two-byte registers is read, the msb and lsb are latched simultaneously and held for the duration of the read data transaction. this prevents register updates during the read and ensures synchronization between the msb and lsb of two byte register values. for consistent results, always read the msb and the lsb of a two-byte register during the same read data transaction. eeprom memory is shadowed by ram to eliminate programming delays between writes and to allow the data to be verified by the host system before being copied to eeprom. the read data and write data protocols to/from eeprom memory addresses access the shadow ram. the recall data function command transfers data from the eeprom to the shadow ram. the copy data function command transfers data from the shadow ram to the eeprom and requires t eec to complete programming of the eeprom cells. in unlocked eeprom blocks, writing data updates shadow ram. in locked eeprom blocks, attempts to write data are ignored. the copy data function command copies the contents of shadow ram to eeprom in an unlocked block of eeprom but has no effect on locked blocks. the recall data function command copies the contents of a block of eeprom to shadow ram regardless of whether the block is locked or not. figure 10. eeprom access via shadow ram serial interface write read shadow ram eeprom copy recall
ds2764 high-precision li+ battery monitor with 2-wire interface 14 of 20 table 2. memory map address (hex) description read/write 00 protection register r/w 01 status register r 02?06 reserved 07 eeprom register r/w 08 special feature register r/w 09?0b reserved 0c voltage register msb r 0d voltage register lsb r 0e current register msb r 0f current register lsb r 10 accumulated current register msb r/w 11 accumulated current register lsb r/w 12?17 reserved 18 temperature register msb r 19 temperature register lsb r 1a?1f reserved 20?2f eeprom, block 0 r/w* 30?3f eeprom, block 1 r/w* 40?47 eeprom, block 2 r/w* 50?ef reserved f0?f7 unique id r + f8?fd reserved fe function command register w ff reserved * each eeprom block is read/write until locked by the lock command, after which it is read-only. + unique 64 bit id is a factory option available by special order. units with ids do not allow access to block 2 of user eeprom protection register the protection register consists of flags that indicate protection circuit status and switches that give conditional control over the charging and discharging paths. bits ov, uv, coc, and doc are set when corresponding protection conditions occur and remain set until cleared by the host system. the default values of the ce and de bits of the protection register are stored in lockable eeprom in the corresponding bits in address 30h. a recall data command for eeprom block 1 recalls the default values into ce and de. figure 11 shows the format of the protection register. the function of each bit is described in detail in the following paragraphs. figure 11. protection register format address 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ov uv coc doc cc dc ce de ov? overvoltage flag. when set to 1, this bit indicates the battery pack has experienced an overvoltage condition. this bit must be reset by the host system. uv ?undervoltage flag. when set to 1, this bit indicates the battery pack has experienced an undervoltage condition. this bit must be reset by the host system. coc ?charge overcurrent flag. when set to 1, this bit indicates the battery pack has experienced a charge- direction overcurrent condition. this bit must be reset by the host system. doc ?discharge overcurrent flag. when set to 1, this bit indicates the battery pack has experienced a discharge- direction overcurrent condition. this bit must be reset by the host system.
ds2764 high-precision li+ battery monitor with 2-wire interface 15 of 20 cc ? cc pin mirror. this read-only bit mirrors the state of the cc output pin. dc ? dc pin mirror. this read-only bit mirrors the state of the dc output pin. ce ?charge enable. writing a 0 to this bit disables charging ( cc output high, external charge fet off) regardless of cell or pack conditions. writing a 1 to this bit enables charging, subject to override by the presence of any protection conditions. the ds2764 automatically sets this bit to 1 when it transitions from sleep mode to active mode. de ?discharge enable. writing a 0 to this bit disables discharging ( dc output high, external discharge fet off) regardless of cell or pack conditions. writing a 1 to this bit enables discharging, subject to override by the presence of any protection conditions. the ds2764 automatically sets this bit to 1 when it transitions from sleep mode to active mode. status register the read-only status register shows the status of bits which enable or disable selected functions of the ds2764. functions are enabled or disabled by programming a default value fo r the corresponding bits in lockable eeprom address 31h. after writing the desired value to 31h, the copy data and recall data commands for eeprom block 1 are required to transfer the default values into the status register bits and activate the selected functions. the selected functions become the default mode of the ds2764 since a recall from block 1 occurs on power-up. the format of the status register is shown in figure 12. figure 12. status register format address 01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x pmod x x x x x x ?reserved bits. pmod? sleep mode enable. a value of 1 in this bit enables the ds2764 to enter sleep mode when the bus is low for greater than 2s and to leave sleep mode when the scl or sda line goes high. a value of 0 disables bus- related transitions into and out of sleep mode. this bit is read-only. the desired default value should be set in bit 5 of address 31h. the factory default is 0. eeprom register the format of the eeprom register is shown in figure 13. the function of each bit is described in detail in the following paragraphs. figure 13. eeprom register format address 07 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eec lock x x x bl2 bl1 bl0 eec ?eeprom copy flag. a 1 in this read-only bit indicates that a copy data or lock function command is in progress. while this bit is high, writes to eeprom addresses are ignored and copy data and lock function commands cannot be issued. a 0 in this bit indicates that data may be written to unlocked eeprom blocks. lock ?eeprom lock enable. when this bit is 0, the lock function command is ignored. writing a 1 to this bit enables the lock function command. after the lock function command is executed, the lock bit is reset to 0. the factory default is 0.
ds2764 high-precision li+ battery monitor with 2-wire interface 16 of 20 bl2? eeprom block 2 lock flag. a 1 in this read-only bit indicates that eeprom block 2 (addresses 40 to 47) is locked (read-only) while a 0 indicates block 2 is unlocked (read/write). the special order unique 64-bit id device does not support eeprom block 2. bl1? eeprom block 1 lock flag. a 1 in this read-only bit indicates that eeprom block 1 (addresses 30 to 3f) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write). bl0? eeprom block 0 lock flag. a 1 in this read-only bit indicates that eeprom block 0 (addresses 20 to 2f) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write). x ?reserved bits. special feature register the format of the special feature register is shown in figure 14. the function of each bit is described in detail in the following paragraphs. figure 14. special feature register format address 08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ps x x x x x sawe x ps ps pin latch. this bit latches a low state on the ps pin with a 0 value. the bit is cleared only by writing a 1 to this location. see the power switch input section. sawe slave address write enable. this bit must be set to 1 before the 2-wire slave address in location 0x32 can be modified. sawe should be written back to 0 after writing the slave address. power up default is 0. x reserved bits. programmable slave address the 2-wire slave address of the ds2764 is stored in lockable eeprom block 1, address 32h. programming the slave address requires a write to set the sawe bit in the special feature register, followed by a write to 32h with the desired slave address. the new slave address value is effective following the write to 32h, and must be used to address the ds2764 on subsequent bus transactions. the slave address value is not stored to eeprom until a copy eeprom block 1 command is executed. prior to executing the copy command, power cycling the ds2764 restores the original slave address value. the data format of the slave address value in address 32h is shown in figure 15. figure 15. slave address format address 32 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a6 a5 a4 a3 a2 a1 a0 x a6 to a0? slave address. a6-a0 contains the 7-bit slave address of the ds2764. the factory default is 0110100b. x ?reserved bits.
ds2764 high-precision li+ battery monitor with 2-wire interface 17 of 20 2-wire bus system the 2-wire bus system supports operation as a slave only device in a single or multi-slave, and single or multi- master system. up to 128 slave devices may share the bus by uniquely setting the 7-bit slave address. the 2-wire interface consists of a serial data line (sda) and serial clock line (scl). sda and scl provide bidirectional communication between the ds2764 slave device and a master device at speeds up to 100khz. the ds2764?s sda pin operates bi-directionally, that is, when the ds2764 receives data, sda operates as an input, and when the ds2764 returns data, sda operates as an open drain output, with the host system providing a resistive pull-up. the ds2764 always operates as a slave device, receiving and transmitting data under the control of a master device. the master initiates all transactions on the bus and generates the scl signal as well as the start and stop bits which begin and end each transaction. bit transfer one data bit is transferred during each scl clock cycle, with the cycle defined by scl transitioning low-to-high and then high-to-low. the sda logic level must remain stable during the high period of the scl clock pulse. any change in sda when scl is high is interpreted as a start or stop control signal. bus idle the bus is defined to be idle, or not busy, when no master device has control. both sda and scl remain high when the bus is idle. the stop condition is the proper method to return the bus to the idle state. start and stop conditions the master initiates transactions with a start condition (s), by forcing a high-to-low transition on sda while scl is high. the master terminates a transaction with a stop condition (p), a low-to-high transition on sda while scl is high. a repeated start condition (sr) can be used in place of a stop then start sequence to terminate one transaction and begin another without returning the bus to the idle state. in multi-master systems, a repeated start allows the master to retain control of the bus. the start and stop conditions are the only bus activities in which the sda transitions when scl is high. acknowledge bits each byte of a data transfer is acknowledged with an acknowledge bit (a) or a no acknowledge bit (n). both the master and the ds2764 slave generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until scl returns low. to generate a no acknowledge (also called nak), the receiver releases sda before the rising edge of the acknowledge-related clock pulse and leaves sda high until scl returns low. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should re-attempt communication. data order a byte of data consists of 8 bits ordered most significant bit (msb) first. the least significant bit (lsb) of each byte is followed by the acknowledge bit. ds2764 registers composed of multi-byte values are ordered most significant byte (msb) first. the msb of multi-byte registers is stored on even data memory addresses. slave address a bus master initiates communication with a slave device by issuing a start condition followed by a slave address (saddr) and the read/write (r/w) bit. when the bus is idle, the ds2764 continuously monitors for a start condition followed by its slave address. when the ds2764 receives a slave address that matches the value in its programmable slave address register, it responds with an acknowledge bit during the clock period following the r/w bit. the 7-bit programmable slave address register is factory programmed to 0110100. the slave address can be re-programmed, refer to the programmable slave address section for details. read/write bit the r/w bit following the slave address determines the data direction of subsequent bytes in the transfer. r/w = 0 selects a write transaction, with the following bytes being written by the master to the slave. r/w = 1 selects a read transaction, with the following bytes being read from the stave by the master.
ds2764 high-precision li+ battery monitor with 2-wire interface 18 of 20 bus timing the ds2764 is compatible with any bus timing up to 100khz. no special configuration is required to operate at any speed. 2-wire command protocols the command protocols involve several transaction formats. the simplest format consists of the master writing the start bit, slave address, r/w bit, and then monitoring the acknowledge bit for presence of the ds2764. more complex formats such as the write data, read data and function command protocols write data, read data and execute device specific operations. all bytes in each command format require the slave or host to return an acknowledge bit before continuing with the next byte. each function command definition outlines the required transaction format. the following key applies to the transaction formats. table 3. 2-wire protocol key key description key description s start bit sr repeated start saddr slave address (7-bit) w r/w bit = 0 fcmd function command byte r r/w bit = 1 maddr memory address byte p stop bit data data byte written by master data data byte returned by slave a acknowledge bit - master a acknowledge bit slave n no acknowledge - master n no acknowledge slave basic transaction formats write: s saddr w a maddr a data0 a p a write transaction transfers one or more data bytes to the ds2764. the data transfer begins at the memory address supplied in the maddr byte. control of the sda signal is retained by the master throughout the transaction, except for the acknowledge cycles. read: s saddr w a maddr a sr saddr r a data0 n p write portion read portion a read transaction transfers one or more bytes from the ds2764. read transactions are composed of two parts, a write portion followed by a read portion, and is therefore inherently longer than a write transaction. the write portion communicates the starting point for the read operation. the read portion follows immediately, beginning with a repeated start, slave address with r/w set to a 1. control of sda is assumed by the ds2764 beginning with the slave address acknowledge cycle. control of the sda signal is retained by the ds2764 throughout the transaction, except for the acknowledge cycles. the master indicates the end of a read transaction by responding to the last byte it requires with a no acknowledge. this signals the ds2764 that control of sda is to remain with the master following the acknowledge clock. write data protocol the write data protocol is used to write to register and shadow ram data to the ds2764 starting at memory address maddr. data0 represents the data written to maddr, data1 represents the data written to maddr + 1 and datan represents the last data byte, written to maddr + n. the master indicates the end of a write transaction by sending a stop or repeated start after receiving the last acknowledge bit. s saddr w a maddr a data0 a data1 a ? datan a p the msb of the data to be stored at address maddr can be written immediately after the maddr byte is acknowledged. because the address is automatically incremented after the least significant bit (lsb) of each byte is received by the ds2764, the msb of the data at address maddr + 1 is can be written immediately after the acknowledgement of the data at address maddr. if the bus master continues an auto-incremented write transaction beyond address 4fh, the ds2764 ignores the data. data is also ignored on writes to read-only addresses and reserved addresses, locked eeprom blocks as well as a write that auto increments to the function command register (address feh). incomplete bytes and bytes that are not acknowledged by the ds2764 are not written to memory. as noted in the memory section, writes to unlocked eeprom blocks modify the shadow ram only.
ds2764 high-precision li+ battery monitor with 2-wire interface 19 of 20 read data protocol the read data protocol is used to read register and shadow ram data from the ds2764 starting at memory address specified by maddr. data0 represents the data byte in memory location maddr, data1 represents the data from maddr + 1 and datan represents the last byte read by the master. s saddr w a maddr a sr saddr r a data0 a data1 a ? datan n p data is returned beginning with the most significant bit (msb) of the data in maddr. because the address is automatically incremented after the least significant bit (lsb) of each byte is returned, the msb of the data at address maddr + 1 is available to the host immediately after the acknowledgement of the data at address maddr. if the bus master continues to read beyond address ffh, the ds2764 outputs data values of ffh. addresses labeled ?reserved? in the memory map return undefined data. the bus master terminates the read transaction at any byte boundary by issuing a no acknowledge followed by a stop or repeated start. function command protocol the function command protocol executes a device specific operation by writing one of the function command values (fcmd) to memory address feh. table 4 lists the ds2764 fcmd values and describes the actions taken by each. a one byte write protocol is used to transmit the function command, with the maddr set to feh and the data byte set to the desired fcmd value. additional data bytes are ignored. data read from memory address feh is undefined. s saddr w a maddr=0feh a fcmd a p table 4. function commands function command target eeprom block fcmd value description 0 42h 1 44h copy data 2 48h this command copies the shadow ram to the target eeprom block. copy data commands that target locked blocks are ignored. while the copy data command is executing, the eec bit in the eeprom register is set to 1, and write data commands with maddr set to any address within the target block are ignored. read data and write data commands with maddr set outside the target block are processed while the copy is in progress. the copy data command execution time, t eec , is 2ms typical and starts after the fcmd byte is acknowledged. subsequent copy or lock commands must be delayed until the eeprom programming cycle completes. 0 b2h 1 b4h recall data 2 b8h this command recalls the contents of the targeted eeprom block to its shadow ram. 0 63h 1 66h lock 2 6ah this command locks (write-protects) the targeted eeprom block. the lock bit in the eeprom register must be set to 1 before the lock command is executed. if the lock bit is 0, the lock command has no effect. the lock command is permanent; a locked block can never be written again. the lock command execution time, t eec , is 2ms typical and starts after the fcmd byte is acknowledged. subsequent copy or lock commands must be delayed until the eeprom programming cycle completes. note: eeprom block 2 is not supported on special order devices with unique ids.
ds2764 high-precision li+ battery monitor with 2-wire interface 20 of 20 64-bit unique id the ds2764 can be special ordered with a unique, factory-programmed id that is 64 bits in length. the first eight bits are the product family code (b0h for ds2764). the next 48 bits are a unique 40-bit serial number followed by 0x64h. the last eight bits are a cyclic redundancy check (crc) of the first 56 bits (see figure 16). the 64-bit id can be read as 8 bytes starting at memory address f0h. the 64-bit id is read only. figure 16. 64-bit id format 8-bit crc 48-bit serial number 8-bit family code (b0h) msb lsb selector guide part marking package information ds2764ae+ ds2764a tssop, external sense resistor, 4.275v v ov ds2764be+ ds2764b tssop, external sense resistor, 4.35v v ov ds2764ae+t&r ds2764a ds2764ae+ on tape-and-reel ds2764be+t&r ds2764b ds2764be+ on tape-and-reel ds2764ae+025* 2764a25 tssop, 25m sense resistor, 4.275v v ov ds2764be+025* 2764b25 tssop, 25m sense resistor, 4.35v v ov ds2764ae+025/t&r* 2764a25 ds2764ae+025 in tape-and-reel ds2764be+025/t&r* 2764b25 ds2764be+025 in tape-and-reel ds2764ax-025/t&r* ds2764ar flip-chip, 25m sense resistor, tape-and-reel, 4.275v v ov ds2764bx-025/t&r* ds2764br flip-chip, 25m sense resistor, tape-and-reel, 4.35v v ov ds2764ax/t&r* ds2764a flip-chip, external sense resistor, tape-and-reel, 4.275v v ov ds2764bx/t&r* ds2764b flip-chip, external sense resistor, tape-and-reel, 4.35v v ov *denotes option available at a future date; contact maxim/dallas semiconductor sales for availability. +denoted lead-free package. note 1: additional v ov options are available, contact maxim/dallas semiconductor sales. note 2: to order devices with the unique 64-bit id option, contact maxim/dallas semiconductor sales. package information (for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and spec ifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa

▲Up To Search▲

Price & Availability of DS2764AE025

	To Download DS2764AE025 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .